The invention relates mainly to techniques for reducing non-linearities and distortion in switched capacitor circuits, especially lossy integrators and 1-bit DACs, and also to techniques for reducing errors caused in reference voltage circuits due to data-dependent currents therein, and even more particularly to reducing non-linearities and errors in a digital-to-analog converter circuit including a 1-bit switched capacitor DAC and a switched capacitor lossy integrator.
By way of background, it is well known that the capacitors used in integrated circuit switched capacitor circuits have capacitances which vary as a function of the voltages across them. The rate of change of the capacitance of such an integrated circuit capacitor over a voltage interval is referred to as its "voltage coefficient of capacitance". The variation in capacitance of such a capacitor during circuit operation can cause undesirable non-linearities in operation of circuits including switched capacitors. U.S. Pat. No. 4,918,454 (Early et al) describes the problem in delta sigma analog-to-digital converters (ADCs) and in CDAC-type DACs. Early et al. provide the solution of connecting two equal, oppositely oriented capacitors in parallel to produce automatic cancellation of the effects of the linear voltage coefficients of the two capacitors. This technique requires that the two capacitors be very precisely matched, which is sometimes difficult to achieve in an integrated circuit manufacturing process. Digital-to-analog converters in which a serial 1-bit code passes through a 1-bit DAC, the output of which is connected to an analog post-filter, are well known. See especially FIG. 6 of "A CMOS Stereo 16-bit D/A Converter for Digital Audio" by Peter J. A. Naus et al., IEEE Journal of Solid-State Circuits, vol. SC-22, pp. 390-395, June 1987.
FIG. 8 of U.S. Pat. No. 4,918,454 shows an analog modulator of a delta-sigma ADC in which a sampling capacitor 106 has its terminals reversed every phase in order to time-average the effects of the voltage coefficient of that sampling capacitor. The switched capacitor sampling circuit includes a "pure", i.e., non-lossy, high gain integrator. FIG. 9 of U.S. Pat. No. 4,918,454 shows an analog modulator of a delta sigma ADC in which two sampling capacitors having their (+) terminals in opposite orientations are used to sample an analog input voltage which is to be converted. FIGS. 10a-d of U.S. Pat. No. 4,918,454 disclose CDAC-type digital-to-analog converters in which the output of a CDAC (capacitor digital-to-analog converter) is provided as an input to a resettable "pure" integrator.
However, those skilled in the art know that a lossy integrator would never be used in either a delta sigma analog-to-digital converter or a CDAC-type of digital-to-analog converter, because in both applications there is a need for high DC gain in the operational amplifier and feedback circuit; use of a lossy integrator in this case would completely defeat the need for the =high DC gain. Therefore, switched capacitor feedback is never used in "pure" integrators (although feedback capacitors of "pure" integrators can be resettable).
In a 1-bit DAC, the 1-bit data input determines whether a high or a low reference voltage gets switched onto the sampling capacitor or capacitors of the 1-bit DAC. Since the 1-bit input data stream contains a large amount of high frequency energy, it is conventional to feed the output of the 1-bit DAC into a filter to begin a filtering process by which unwanted high frequency noise is removed.
In the CDAC-type analog-to-digital converters shown in FIGS. 10a-d of U.S. Pat. No. 4,918,454, charge in the capacitive CDAC array is redistributed according to a multi-bit binary weighted signal to transfer charge onto the switched feedback capacitors of the lossy integrator. Those skilled in the art will appreciate that in a CDAC-type of digital-to-analog converter, the converted analog output appears almost immediately, but that the linearity of such a digital-to-analog converter is determined by matching of various capacitors in the CDAC array. In contrast, the 1-bit DAC type digital-to-analog converter is inherently linear and monotonic, and its output can be configured to any desired resolution, i.e., to any desired number of bits.
To improve capacitive matching in capacitors of a CDAC array, expensive trimming circuit techniques are required. In contrast, in 1-bit DACs, any mismatch between the capacitors of the DAC appears as a DC offset voltage that can be easily filtered out, and does not effect the linearity of the 1-bit digital-to-analog converter.
Thus, those skilled in the art know that a CDAC-type of digital-to-analog converter is used in entirely different applications than a 1-bit DAC type of digital-to-analog converter, in which the analog output is a time-averaged representation of the serial string of data constituting the 1-bit digital input.
There is a standard technique generally referred to as "bottom plate sampling" used in a switched capacitor integrator circuit wherein the switches connected to the capacitors on the integrating node side of the switches are switched off before the switches connected to the other plates of the capacitors, to reduce data-dependent charge injection into the integrating node. This technique generally requires a number of variously delayed clock signals, which can be readily provided by those skilled in the art using conventional circuit techniques.
Delta sigma modulator based DACs are a popular way to implement high resolution digital-to-analog converters, especially in mixed signal integrated circuits. Often these DACs use switched capacitor circuits in the signal path to provide low power, well matched components, and good dynamic range. In particular, the so-called 1-bit DAC is very common because of its inherently linear structure. However, one of the limitations to the linearity of the signal transfer function of a 1-bit delta-sigma DAC is the non-linearity of the capacitors used to implement the filter. Normally, the first order term of the voltage coefficient of the capacitors is dominant, and a number of methods have been proposed to overcome this problem, including balancing the doping of the two double polycrystaline silicon layers used to form the capacitors, the use of fully differential circuits, and using differently oriented parallel-connected capacitors as disclosed in U.S. Pat. No. 4,918,454 (Early et al.).
However, balancing the doping levels of the polycrystaline silicon layers may be incompatible with the processing of the transistors; where a silicide layer is used, the use of the second layer as a resistor or just use of an additional mask to control the silicide growth increases costs. Use of fully differential circuits requires more complex operational amplifiers, with a subsequent increase in power dissipation and chip area. The use of two differently oriented capacitors in parallel to cancel effects of the voltage coefficient is limited by the matching of the two capacitors.
In switched capacitor circuits one or both terminals of a switched capacitor may be switched to a reference voltage, causing a flow of charge between the capacitor and a reference voltage circuit producing the reference voltage. The flow of charge through the output impedance of the reference voltage circuit causes an error that is added to the reference voltage, and if the charge is data-dependent, the error in the reference voltage also is data-dependent. This distorts the signal information being processed by the switched capacitor circuit. There is an unmet need for a solution to this problem.